1.7. Test Register

Two special registers are provided for validation purposes: Timer1Test and Timer2Test. These locations should not be accessed during normal operation.

Both registers are read-write and are 2 bits wide:

Table 1.3. Test register bit functions




Counter Test Mode



Test Clock Select

When the Counter Test Mode bit is set, the 16-bit counter of the selected timer is divided into four separate 4-bit counters that continually loop round from 15 to 0. This ensures the correct counting sequence is performed. Clearing this bit (default) brings the selected timer back to normal operation.

When the Test Clock Select bit is set in any of the two test registers, a special test clock (PSTB ANDed with PSEL) is fed into the prescale unit instead of the system clock. Clearing this bit (default) selects the system clock as the prescale clock input (normal operation).

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