This appendix describes in more detail the debug features of the ARM7TDMI-S and includes additional information about the EmbeddedICE macrocell. It contains the following sections:
Scan chains and JTAG interface
Scan chain implementation
Resetting the TAP controller
Instruction register
Public instructions
Test data registers
ARM7TDMI‑S core clock domains
Determining the core and system state
Behavior of the program counter during debug
Priorities and exceptions
Scan interface timing
The watchpoint registers
Programming breakpoints
Programming watchpoints
The debug control register
The debug status register
Coupling breakpoints and watchpoints
Disabling EmbeddedICE
EmbeddedICE timing.