Instruction

Description

{cond}

See Table 1‑11 on page ‑17.

<Oprnd2>

See Table 1‑9 on page ‑16.

{field}

See Table 1‑10 on page ‑16.

S

Sets condition codes (optional).

B

Byte operation (optional).

H

Halfword operation (optional).

T

Forces address translation. Cannot be used with pre‑indexed addresses.

<a_mode2>

See Table 1‑3 on page ‑13.

<a_mode2P>

See Table 1‑4 on page ‑14.

<a_mode3>

See Table 1‑5 on page ‑14.

<a_mode4L>

See Table 1‑6 on page ‑15.

<a_mode4S>

See Table 1‑7 on page ‑15.

<a_mode5>

See Table 1‑8 on page ‑15.

#32bit_Imm

A 32‑bit constant, formed by right‑rotating an 8‑bit value by an even number of bits.

<reglist>

A comma-separated list of registers, enclosed in braces ( { and } ).