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A Coprocessor Data Processing (CDP) operation is a request from the ARM7TDMI-S for the coprocessor to initiate some action. There is no need to complete the action immediately, but the coprocessor must commit to completion before driving CPB LOW.
If the coprocessor cannot perform the requested task, it leaves CPA and CPB HIGH. When the coprocessor is able to perform the task, but cannot commit immediately, the coprocessor drives CPA LOW, but leaves CPB HIGH until able to commit. The ARM7TDMI-S busy-waits until CPB goes LOW. However, an interrupt might cause the ARM7TDMI-S to abandon a busy‑waiting coprocessor instruction (see Consequences of busy‑waiting).
The coprocessor data operations cycle timings are listed in Table 6.17.
Table 6.17. Coprocessor data operation instruction cycle operations
Cycle | Address | Write | Size | Data | TRANS[1:0] | Prot0 | CPnI | CPA | CPB | |
|---|---|---|---|---|---|---|---|---|---|---|
ready | 1 | pc+8 | 0 | w | (pc+8) | N cycle | 0 | 0 | 0 | 0 |
pc+12 | ||||||||||
not ready | 1 | pc+8 | 0 | w | (pc+8) | I cycle | 0 | 0 | 0 | 1 |
2 | pc+8 | 0 | w | - | I cycle | 1 | 0 | 0 | 1 | |
• | pc+8 | 0 | w | - | I cycle | 1 | 0 | 0 | 1 | |
n | pc+8 | 0 | w | - | N cycle | 1 | 0 | 0 | 0 | |
pc+12 |
Coprocessor operations are available only in ARM state.
| Copyright © ARM Limited 1998-2000. All rights reserved. | ARM DDI 0084F |
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| Home > Instruction Cycle Timings > Coprocessor data processing operation |