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The Move fRom Coprocessor (MRC) operation reads a single coprocessor register into the specified ARM register.
Data is transferred in the second cycle and written to the ARM register during the third cycle of the operation.
If the coprocessor signals busy-wait by asserting CPB, an interrupt can cause the ARM7TDMI-S to abandon the coprocessor instruction (see Consequences of busy‑waiting).
As is the case with all ARM7TDMI-S register load instructions, the ARM7TDMI-S might merge the third cycle with the following prefetch cycle into a merged I-S cycle.
The MRC cycle timings are listed in Table 6.20.
Table 6.20. Coprocessor register transfer (MRC)
Cycle | Address | Size | Write | Data | TRANS[1:0] | Prot0 | CPnI | CPA | CPB | |
|---|---|---|---|---|---|---|---|---|---|---|
ready | 1 | pc+8 | w | 0 | (pc+8) | C cycle | 0 | 0 | 0 | 0 |
2 | pc+12 | w | 0 | CPdata | I cycle | 1 | 1 | 1 | 1 | |
3 | pc+12 | w | 0 | - | S cycle | 1 | 1 | - | - | |
pc+12 | ||||||||||
not ready | 1 | pc+8 | w | 0 | (pc+8) | I cycle | 0 | 0 | 0 | 1 |
2 | pc+8 | w | 0 | - | I cycle | 1 | 0 | 0 | 1 | |
• | pc+8 | w | 0 | - | I cycle | 1 | 0 | 0 | 1 | |
n | pc+8 | w | 0 | - | C cycle | 1 | 0 | 0 | 0 | |
n+1 | pc+12 | w | 0 | CPdata | I cycle | 1 | 1 | 1 | 1 | |
n+2 | pc+12 | w | 0 | - | S cycle | 1 | 1 | - | - | |
pc+12 | ||||||||||
This operation cannot occur in Thumb state.
| Copyright © ARM Limited 1998-2000. All rights reserved. | ARM DDI 0084F |
| Non-Confidential | |
| PDF version | |
| Home > Instruction Cycle Timings > Coprocessor register transfer (move from coprocessor to ARM register) |