ARM7TDMI-S Technical Reference Manual 6.13. Software interrupt, and exception entry

6.13. Software interrupt, and exception entry

Exceptions, and SoftWare Interrupts (SWIs) force the PC to a specific value, and refill the instruction pipeline from this address:

During the first cycle, the ARM7TDMI-S constructs the forced address, and a mode change might take place. The ARM7TDMI-S moves the return address to r14 and moves the CPSR to SPSR_svc.
During the second cycle, the ARM7TDMI-S modifies the return address to facilitate return (although this modification is less useful than in the case of branch with link).
The third cycle is required only to complete the refilling of the instruction pipeline.

The SWI cycle timings are listed in Table 6.16, where:

s: Represents the current supervisor mode dependent value.
t: Represents the current Thumb state value.
pc: Is, for software interrupts, the address of the SWI instruction. For exceptions, this is the address of the instruction following the last one to be executed before entering the exception. For Prefetch Aborts, this is the address of the aborting instruction. For Data Aborts, this is the address of the instruction following the one that attempted the aborted data transfer.
Xn: Is the appropriate trap address.

Table 6.16. Software interrupt instruction cycle operations

Cycle	Address	Size	Write	Data	TRANS[1:0]	Prot0	Prot1	Mode	Tbit
1	pc+2i	w/h	0	(pc+2i)	N cycle	0	s	old mode	t
2	Xn	w’	0	(Xn)	S cycle	0	1	exception mode	0
3	Xn+4	w’	0	(Xn+4)	S cycle	0	1	exception mode	0
	Xn+8

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