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Table 2‑3 summarizes the PC value preserved in the relevant r14 on exception entry and the recommended instruction for exiting the exception handler.
Table 2.3. Exception entry and exit
Exception or entry | Return instruction | Previous state | Notes | |
|---|---|---|---|---|
ARM r14_x | Thumb r14_x | |||
BL | MOV PC, R14 | PC + 4 | PC + 2 | Where the PC is the address of the BL, SWI, undefined instruction Fetch, or instruction that had the Prefetch Abort. |
SWI | MOVS PC, R14_svc | PC + 4 | PC + 2 | |
Undefined instruction | MOVS PC, R14_und | PC + 4 | PC + 2 | |
Prefetch Abort | SUBS PC, R14_abt, #4 | PC + 4 | PC + 4 | |
FIQ | SUBS PC, R14_fiq, #4 | PC + 4 | PC + 4 | Where the PC is the address of the instruction that was not executed because the FIQ or IRQ took priority. |
IRQ | SUBS PC, R14_irq, #4 | PC + 4 | PC + 4 | |
Data Abort | SUBS PC, R14_abt, #8 | PC + 8 | PC + 8 | Where the PC is the address of the Load or Store instruction that generated the Data Abort. |
RESET | Not applicable | - | - | The value saved in r14_svc on reset is |
| Copyright © ARM Limited 1998-2000. All rights reserved. | ARM DDI 0084F |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Exceptions > Exception entry/exit summary |