ARM7TDMI-S Technical Reference Manual C.15. The debug status register

C.15. The debug status register

The debug status register is 5 bits wide. If it is accessed for a write (with the read/write bit set HIGH), the status bits are written. If it is accessed for a read (with the read/write bit LOW), the status bits are read. The format of the debug status register is shown in Figure C.9.

Figure C.9. Debug status register format

The function of each bit in this register is as follows:

Bit 4: Allows TBIT to be read. This enables the debugger to determine the processor state and therefore which instructions to execute.
Bit 3: Allows the state of the TRANS[1] signal from the core to be read. This state allows the debugger to determine whether a memory access from the debug state has completed.
Bit 2: Allows the state of the core interrupt enable signal (IFEN) to be read.
Bits 1:0: Allow the values on the synchronized versions of DBGRQ and DBGACK to be read.

The structure of the debug control and status registers is shown in Figure C.10.

Figure C.10. Debug control and status register structure

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