C.1.2. TAP state machine

The process of serial test and debug is best explained in conjunction with the JTAG state machine. Figure C.2 shows the state transitions that occur in the TAP controller.

Figure C.2. Test access port controller state transitions

From IEEE Std 1149.1-1990. Copyright 1999 IEEE. All rights reserved.

Copyright © ARM Limited 1998-2000. All rights reserved.ARM DDI 0084F
Non-Confidential