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| Home > Differences Between the ARM7TDMI‑S and the ARM7TDMI > ARM7TDMI‑S design considerations > Interrupt timing | |||
As with all ARM7TDMI-S signals, the interrupt signals nIRQ and nFIQ are sampled on the rising edge of CLK.
When you are converting an ARM7TDMI hard macrocell design where the ISYNC signal is asserted LOW, add a synchronizer to the design to synchronize the interrupt signals before they are applied to the ARM7TDMI-S.