ARM7TDMI-S Technical Reference Manual 7.1. Timing diagrams

7.1. Timing diagrams

The timing diagrams in this section are:

Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5.

Figure 7.1. Timing parameters

Note

The timing for both read and write data access are superimposed in the figure. The WRITE signal conveys whether the access uses the read RDATA or WDATA port.

CLKEN LOW stretches the data access when the read or write transaction is unable to complete within a single cycle.

The data buses are used for transfer only when the transaction signals TRANS[1:0] indicate a valid memory cycle or a coprocessor register transfer cycle.

Figure 7.2. Coprocessor timing

Figure 7.3. Exception and configuration input timing

Figure 7.4. Debug timing

Note

DBGBREAK is sampled on rising clock, so external data-dependent breakpoints and watchpoints must be matched and signaled by this edge.

Figure 7.5. Scan timing

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