1.1.1. The instruction pipeline

The ARM7TDMI-S uses a pipeline to increase the speed of the flow of instructions to the processor. This allows several operations to take place simultaneously, and the processing, and memory systems to operate continuously.

A three-stage pipeline is used, so instructions are executed in three stages:

The three-stage pipeline is shown in Figure 1.1.

Figure 1.1. The instruction pipeline


The Program Counter (PC) points to the instruction being fetched rather than to the instruction being executed.

During normal operation, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

Copyright © ARM Limited 1998-2000. All rights reserved.ARM DDI 0084F