A nonsequential cycle is the simplest form of an ARM7TDMI-S bus cycle, and occurs when the ARM7TDMI-S requests a transfer to or from an address that is unrelated to the address used in the preceding cycle.The memory controller must initiate a memory access to satisfy this request.

The address class signals, and the TRANS[1:0] = N cycle are broadcast on the bus. At the end of the next bus cycle the data is transferred between the CPU, and the memory. This is illustrated in Figure 3.2.

The ARM7TDMI-S can perform back to back nonsequential memory cycles. This happens, for example, when an STR instruction is executed, as shown in Figure 3.3. If you are designing a memory controller for the ARM7TDMI-S, and your memory system is unable to cope with this case, you must use the CLKEN signal to extend the bus cycle to allow sufficient cycles for the memory system. See Using CLKEN to control bus cycles.