A request on one of the external debug interface signals, or on an internal functional unit known as the EmbeddedICE macrocell, forces the ARM7TDMI-S into debug state. The interrupts that activate debug are:

The internal state of the ARM7TDMI-S is examined using a JTAG‑style serial interface, which allows instructions to be serially inserted into the core pipeline without using the external data bus. So, for example, when in debug state, a STore Multiple (STM) can be inserted into the instruction pipeline and this exports the contents of the ARM7TDMI-S registers. This data can be serially shifted out without affecting the rest of the system.