ARM7TDMI-S Technical Reference Manual

(Rev 3)

Table of Contents

About this document
Intended audience
Typographical conventions
Timing diagram conventions
Further reading
ARM publications
Other publications
Feedback on this document
Feedback on the ARM7TDMI‑S
1. Introduction
1.1. About the ARM7TDMI‑S
1.1.1. The instruction pipeline
1.1.2. Memory access
1.1.3. Memory interface
1.2. ARM7TDMI‑S architecture
1.2.1. Instruction compression
1.2.2. The Thumb instruction set
1.3. ARM7TDMI‑S block, core and functional diagrams
1.4. ARM7TDMI‑S instruction set summary
1.4.1. ARM instruction summary
1.4.2. Thumb instruction summary
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor operating states
2.2.1. Switching state
2.3. Memory formats
2.3.1. Big-endian format
2.3.2. Little-endian format
2.4. Instruction length
2.5. Data types
2.6. Operating modes
2.7. Registers
2.7.1. The ARM state register set
2.7.2. The Thumb state register set
2.7.3. The relationship between ARM state and Thumb state registers
2.7.4. Accessing high registers in Thumb state
2.8. The program status registers
2.8.1. The condition code flags
2.8.2. The control bits
2.8.3. Reserved bits
2.9. Exceptions
2.9.1. Exception entry/exit summary
2.9.2. Entering an exception
2.9.3. Leaving an exception
2.9.4. Fast interrupt request
2.9.5. Interrupt request
2.9.6. Abort
2.9.7. Software interrupt instruction
2.9.8. Undefined instruction
2.9.9. Exception vectors
2.9.10. Exception priorities
2.10. Interrupt latencies
2.10.1. Maximum interrupt latencies
2.10.2. Minimum interrupt latencies
2.11. Reset
3. Memory Interface
3.1. About the memory interface
3.2. Bus interface signals
3.3. Bus cycle types
3.3.1. Nonsequential cycles
3.3.2. Sequential cycles
3.3.3. Internal cycles
3.3.4. Merged I‑S cycles
3.3.5. Coprocessor register transfer cycles
3.4. Addressing signals
3.4.1. ADDR[31:0]
3.4.2. WRITE
3.4.3. SIZE[1:0]
3.4.4. PROT[1:0]
3.4.5. LOCK
3.4.6. CPTBIT
3.5. Data timed signals
3.5.1. WDATA[31:0]
3.5.2. RDATA[31:0]
3.5.3. ABORT
3.5.4. Byte and halfword accesses
3.6. Using CLKEN to control bus cycles
4. Coprocessor Interface
4.1. About coprocessors
4.1.1. Coprocessor availability
4.2. Coprocessor interface signals
4.3. Pipeline following signals
4.4. Coprocessor interface handshaking
4.4.1. The coprocessor
4.4.2. The ARM7TDMI‑S
4.4.3. Coprocessor signaling
4.4.4. Consequences of busy‑waiting
4.4.5. Coprocessor register transfer instructions
4.4.6. Coprocessor data operations
4.4.7. Coprocessor load and store operations
4.5. Connecting coprocessors
4.5.1. Connecting a single coprocessor
4.5.2. Connecting multiple coprocessors
4.6. Not using an external coprocessor
4.7. Undefined instructions
4.8. Privileged instructions
5. Debug Interface
5.1. About the debug interface
5.1.1. Stages of debug
5.1.2. Clocks
5.2. Debug systems
5.2.1. The debug host
5.2.2. The protocol converter
5.2.3. The ARM7TDMI-S
5.3. Debug interface signals
5.3.1. Entry into debug state
5.4. ARM7TDMI‑S core clock domains
5.5. Determining the core and system state
5.6. About EmbeddedICE
5.7. Disabling EmbeddedICE
5.8. The debug communications channel
5.8.1. Debug comms channel registers
5.8.2. Communications via the comms channel
6. Instruction Cycle Timings
6.1. About the instruction cycle timings
6.2. Instruction cycle count summary
6.3. Branch and ARM branch with link
6.4. Thumb branch with link
6.5. Branch and exchange
6.6. Data operations
6.7. Multiply, and multiply accumulate
6.8. Load register
6.9. Store register
6.10. Load multiple registers
6.11. Store multiple registers
6.12. Data swap
6.13. Software interrupt, and exception entry
6.14. Coprocessor data processing operation
6.15. Load coprocessor register (from memory to coprocessor)
6.16. Store coprocessor register (from coprocessor to memory)
6.17. Coprocessor register transfer (move from coprocessor to ARM register)
6.18. Coprocessor register transfer (move from ARM register to coprocessor)
6.19. Undefined instructions and coprocessor absent
6.20. Unexecuted instructions
7. AC Parameters
7.1. Timing diagrams
7.2. AC timing parameter definitions
A. Signal Descriptions
A.1. Signal descriptions
B. Differences Between the ARM7TDMI‑S and the ARM7TDMI
B.1. Interface signals
B.2. ATPG scan interface
B.3. Timing parameters
B.4. ARM7TDMI‑S design considerations
B.4.1. Master clock
B.4.2. JTAG interface timing
B.4.3. TAP controller
B.4.4. Interrupt timing
B.4.5. Address class signal timing
B.4.6. ARM7TDMI signals not implemented on ARM7TDMI-S
C. Debug in Depth
C.1. Scan chains and JTAG interface
C.1.1. Scan chain implementation
C.1.2. TAP state machine
C.2. Resetting the TAP controller
C.3. Instruction register
C.4. Public instructions
C.4.1. SCAN_N (0010)
C.4.2. INTEST (1100)
C.4.3. IDCODE (1110)
C.4.4. BYPASS (1111)
C.4.5. RESTART (0100)
C.5. Test data registers
C.5.1. Bypass register
C.5.2. ARM7TDMI‑S device identification (ID) code register
C.5.3. Instruction register
C.5.4. Scan path select register
C.5.5. Scan chains 1 and 2
C.6. ARM7TDMI‑S core clock domains
C.7. Determining the core and system state
C.7.1. Determining the core state
C.7.2. Determining system state
C.7.3. Exit from debug state
C.8. Behavior of the program counter during debug
C.8.1. Breakpoints
C.8.2. Watchpoints
C.8.3. Watchpoint with another exception
C.8.4. Debug request
C.8.5. System speed access
C.8.6. Summary of return address calculations
C.9. Priorities and exceptions
C.9.1. Breakpoint with Prefetch Abort
C.9.2. Interrupts
C.9.3. Data Aborts
C.10. Scan interface timing
C.10.1. Scan chain 1 cells
C.11. The watchpoint registers
C.11.1. Programming and reading watchpoint registers
C.11.2. Using the data, and address mask registers
C.11.3. The control registers
C.12. Programming breakpoints
C.12.1. Hardware breakpoints
C.12.2. Software breakpoints
C.13. Programming watchpoints
C.14. The debug control register
C.15. The debug status register
C.16. Coupling breakpoints and watchpoints
C.16.1. Breakpoint and watchpoint coupling example
C.16.2. DBGRNG signal
C.17. Disabling EmbeddedICE
C.18. EmbeddedICE timing

List of Tables

1.1. Key to tables
1.2. ARM instruction summary
1.3. Addressing mode 2
1.4. Addressing mode 2 (privileged)
1.5. Addressing mode 3
1.6. Addressing mode 4 (load)
1.7. Addressing mode 4 (store)
1.8. Addressing mode 5
1.9. Oprnd2
1.10. Fields
1.11. Condition fields
1.12. Thumb instruction summary
2.1. Register mode identifiers
2.2. PSR mode bit values
2.3. Exception entry and exit
2.4. Exception vectors
3.1. Cycle types
3.2. Burst types
3.3. Transfer widths
3.4. PROT[1:0] encoding
3.5. Transfer size encoding
3.6. Significant address bits
3.7. Word accesses
3.8. Halfword accesses
3.9. Byte accesses
4.1. Coprocessor availability
4.2. Handshaking signals
4.3. Handshake signal connections
4.4. CPnTRANS signal meanings
6.1. Transaction types
6.2. Instruction cycle counts
6.3. Branch instruction cycle operations 
6.4. Thumb long branch with link 
6.5. Branch and exchange instruction cycle operations  
6.6. Data operation instruction cycle operations  
6.7. Multiply instruction cycle operations 
6.8. Multiply-accumulate instruction cycle operations 
6.9. Multiply long instruction cycle operations  
6.10. Multiply-accumulate long instruction cycle operations 
6.11. Load register instruction cycle operations 
6.12. Store register instruction cycle operations 
6.13. Load multiple registers instruction cycle operations
6.14. Store multiple registers instruction cycle operations   
6.15. Data swap instruction cycle operations 
6.16. Software interrupt instruction cycle operations  
6.17. Coprocessor data operation instruction cycle operations 
6.18. Load coprocessor register instruction cycle operations 
6.19. Store coprocessor register instruction cycle operations 
6.20. Coprocessor register transfer (MRC)  
6.21. Coprocessor register transfer (MCR)  
6.22. Undefined instruction cycle operations 
6.23. Unexecuted instruction cycle operations 
7.1. Provisional AC parameters
A.1. Signal descriptions
B.1. ARM7TDMI-S signals and ARM7TDMI hard macrocell equivalents
C.1. Public instructions
C.2. Scan chain number allocation
C.3. Scan chain 1 cells
C.4. Function and mapping of EmbeddedICE registers
C.5. SIZE[1:0] signal encoding
C.6. Interrupt signal control

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Confidentiality Status

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Product Status

The information in this document is Preliminary (information on a product under development).

Revision History
Revision EMarch 1999Major edits, and sections rewritten.
Revision FSeptember 2000Technical and editorial changes.
Copyright © ARM Limited 1998-2000. All rights reserved.ARM DDI 0084F