2.3. JTAG Signals

Table 2.3. JTAG signal descriptions

NameTypeDescription
HIGHZOutHigh ZThis signal denotes that the HIGHZ instruction has been loaded into TAP controller.
IR[3:0]OutTAP Instruction RegisterThese signals reflect the current instruction loaded into the TAP controller instruction register. The signals change on the falling edge of XTCK when the TAP state machine is in the UPDATEDR state. These signals may be used to allow more scan chains to be added using the ARM720T TAP controller.
RSTCLKBSOutReset Boundary Scan ClockThis signal denotes that either the TAP controller state machine is in the RESET state or that XNTRST has been asserted. This may be used to reset boundary scan cells outside the ARM720T
SCREG[3:0]OutScan Chain RegisterThese signals reflect the ID number of the scan chain currently selected by the TAP controller. These signals change on the falling edge of XTCK when the TAP state machine is in the UPDATE-DR state.
SDINBSOutBoundary Scan Serial Data InThis signal is the serial data to be applied to an external scan chain.
SDOUTBSOutBoundary Scan Serial Data OutThis signal is the serial data from an external scan chain. It allows a single XTDO port to be used. If an external scan chain is not connected, this input should be tied LOW.
TAPSM[3:0]OutTap Controller StatusThese signals represent the current state of the TAP controller machine. These signals change on the rising edge of XTCK and may be used to allow more scan chains to be added using the ARM720T TAP controller.
TCK1OutTest Clock 1This clock represents the HIGH phase of XTCK. TCK1 is HIGH when XTCK is HIGH. This signal may be used to allow more scan chains to be added using the ARM720T TAP controller.
TCK2OutTest Clock 2This clock represents the LOW phase of XTCK. TCK2 is HIGH when XTCK is LOW. This signal may be used to allow more scan chains to be added using the ARM720T TAP controller. TCK2 is the non-overlapping complement of TCK1.
XnTDOENOutNot Test Data Out Output EnableWhen LOW, this signal denotes that serial data is being driven out on the XTDO output.
XNTRSTInNot Test ResetWhen LOW, this signal resets the JTAG interface.
XTCKInTest ClockThis signal is the JTAG test clock.
XTDIInTest Data InJTAG test data in signal.
XTDOOutTest Data OutJTAG test data out signal.
XTMSInTest Mode selectJTAG test mode select signal.
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