8.12. Scan Interface Timing

Figure 8.7. Scan general timing

In the following table, all units are ns. All delays are provisional and assume a process which achieves 33MHz MCLK maximum operating frequency.

Table 8.2. Scan interface timing

SymbolParameterMinTypeMaxNotes
Tbscl TCK low period15.1    
Tbsch TCK high period15.1  
TbsisTDI,TMS setup to [TCr]0    
Tbsih TDI,TMS hold from [TCr]0.9    
Tbsoh TDO hold time2.4  2
Tbsod TCr to TDO valid  16.42
Tbsss I/O signal setup to [TCr]3.6  1
Tbssh I/O signal hold from [TCr]7.6  1
Tbsdh data output hold time2.4  2
Tbsdd TCf to data output valid  17.12
Tbsr Reset period25   
TbseOutput Enable time  16.42
TbszOutput Disable time  14.72
Notes
  1. For correct data latching, the I/O signals (from the core and the pads) must be setup and held with respect to the rising edge of TCK in the CAPTURE-DR state of the INTEST and EXTEST instructions.

  2. Assumes that the data outputs are loaded with the AC test loads.

I

Input

O

Output

I/O

Input/Output

Table 8.3. Scan Chain 0: Signals and position

NoSignalType NoSignalType
1D[0]I/O 29D[28]I/O
2D[1]I/O 30D[29]I/O
3D[2]I/O 31D[30]I/O
4D[3]I/O 32D[31]I/O
5D[4]I/O 33BREAKPTI
6D[5]I/O 34NENINI
7D[6]I/O 35NENOUTO
8D[7]I/O 36LOCKO
9D[8]I/O 37BIGENDI
10D[9]I/O 38DBEI
11D[10]I/O 39MAS[0]O
12D[11]I/O 40MAS[1]O
13D[12]I/O 41BL[0]I
14D[13]I/O 42BL[1]I
15D[14]I/O 43BL[2]I
16D[15]I/O 44BL[3]I
17D[16]I/O 45DCTL **O
18D[17]I/O 46nRWO
19D[18]I/O 47DBGACKO
20D[19]I/O 48CGENDBGACKO
21D[20]I/O 49nFIQI
22D[21]I/O 50nIRQI
23D[22]I/O 51nRESETI
24D[23]I/O 52ISYNCI
25D[24]I/O 53DBGRQI
26D[25]I/O 54ABORTI
27D[26]I/O 55CPAI
28D[27]I/O 56nOPCO
57IFENI 82A[23]O
58nCPIO 83A[22]O
59nMREQO 84A[21]O
60SEQO 85A[20]O
61nTRANSO 86A[19]O
62CPBI 87A[18]O
63nM[4]O 88A[17]O
64nM[3]O 89A[16]O
65nM[2]O 90A[15]O
66nM[1]O 91A[14]O
67nM[0]O 92A[13]O
68nEXECO 93A[12]O
69ALEI 94A[11]O
70ABEI 95A[10]O
71APEI 96A[9]O
72TBITO 97A[8]O
73nWAITI 98A[7]O
74A[31]O 99A[6]O
75A[30]O 100A[5]O
76A[29]O 101A[4]O
77A[28]O 102A[3]O
78A[27]O 103A[2]O
79A[26]O 104A[1]O
80A[25]O 105A[0]O
81A[24]O    

Note

DCTL is not described in this datasheet. DCTL is an output from the processor used to control the unidirectional data out latch, DOUT[31:0]. This signal is not visible from the periphery of ARM7DMT.

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