2.1. AMBA Interface Signals

Table 2.1. ASB signal descriptions

NameType

Source/

Destination

Description
AGNTInArbiterAccess Grant.This signal from the bus arbiter indicates that the bus master is currently the highest priority master requesting the bus. If AGNT is asserted at the end of a transfer (BWAIT LOW), the master is granted the bus AGNT changes during the low phase of BCLK, and remains valid through the high phase.
AREQOutArbiterAccess RequestThis signal indicates that the master requires the bus. It changes during the high phase of BCLK. This signal is intended for use where the ARM720T is not the lowest priority or default bus master.
BA[31:0]OutCurrent bus masterBus Address.This is the system address bus
BCLKIn System (bus) ClockThis clock times all bus transfers.
BD[31:0]InOutBus masterBidirectional system data busThis is the data bus is driven by the current bus master during write cycles, and by the appropriate bus slave during read cycles.
BERRORInOutSystem decoder and current bus masterBus ErrorThis signal indicates a transfer error by the selected bus slave using the BERROR signal. When BERROR is HIGH, a transfer error has occurred. When BERROR is LOW, the transfer is successful. This signal is also used in combination with the BLAST signal to indicate a bus retract operation.
BLASTInOutSystem decoder and current bus masterBus ClassThis signal is driven by the selected slave to indicate if the current transfer should be the last of a burst sequence. When BLAST is HIGH the next bus transfer must allow for sufficient time for address decoding. When BLAST is LOW, the next transfer may continue as a burst sequence. This signal is also used in combination with the BERROR signal to indicate a bus retract operation.
BLOKOutArbiterBus ClockWhen HIGH, this signal indicates that the following bus transfer is to be indivisible and no other bus master should be given access to the bus.
BnRESInReset state machineBus ResetThis signal indicates the reset status of the bus.
BPROT[1:0]OutSystem decoderBus ProtectionsThese signals provide additional information about the transfer being performed. All write cycles are indicated as being Supervisor accesses. These signals have the same timing as the BA signals.
BSIZE[1:0]OutCurrent bus masterBus SizeThese signals indicate the size of the transfer, which may be byte, halfword or word. These signals have the same timing as the address bus.
BTRAN[1:0]OutBus masterBus Transaction TypeThese signals indicate the type of the next transaction which may be address-only, nonsequential or sequential. These signals are driven when AGNT is asserted, and are valid during the high phase of BCLK before the transfer to which they refer.
BWAITInOutSystem decoder and current bus masterBus WaitThis signal is driven by the selected slave to indicate if the current transfer may complete. If BWAIT is HIGH, a further bus cycle is required. If BWAIT is LOW, the current transfer may complete in the current bus cycle.
BWRITEInOutCurrent bus masterBus WriteWhen HIGH, this signal indicates a bus write cycle and when LOW, a read cycle. This signal has the same timing as the address bus.
DSELInSystem decoderSlave SelectThis signal puts the ARM core into a test mode so that vectors can be written in and out of the core.
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