11.8. Read-Lock-Write

The read-lock-write sequence is generated by a SWP instruction.

The BLOK signal indicates that the two accesses should be treated as an atomic unit. A memory controller should ensure that no other bus activity is allowed to happen between the accesses when BLOK is asserted. When the ARM has started a read‑lock-write sequence, it cannot be interrupted until it has completed.

On the bus, the sequence consists of:

This sequence is differentiated by the BLOK signal. BLOK:

The read cycle is always performed as a single, non-sequential, external read cycle, regardless of the contents of the cache.

The write is forced to be unbuffered, so that it can be aborted if necessary.

The cache is updated on the write.

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