8.4. Scan Chains and JTAG Interface

There are three JTAG style scan chains inside ARM7DMT and an additional scan chain inside ARM720T. These allow testing, debugging, and EmbeddedICE programming.

In addition, support is provided for an optional fourth scan chain. This is intended to be used for an external boundary scan chain around the pads of a packaged device. The control signals provided for this scan chain are described later.

The scan chains are controlled from a JTAG‑style Test Access Port (TAP) controller. For further details of the JTAG specification, please refer to IEEE Standard 1149.1-1990 “Standard Test Access Port and Boundary-Scan Architecture”.


The scan cells are not fully JTAG-compliant. The following sections describe the limitations on their use.

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