11.3. Addressing Signals

Memory accesses may be read or write, and are differentiated by the signal BWRITE.

BWRITE may not change during a sequential access, so if a read from address A is followed immediately by a write to address (A+4), the write to address (A+4) is performed on the bus as a non-sequential access.

In the same way, any memory access may be a word, a half-word or a byte. These are differentiated by the signal BSIZE[1:0]. Again, BSIZE[1:0] may not change during sequential accesses. It is not possible to perform sequential byte accesses.

In order to reduce system power consumption, the addressing signals are left with their current values at the end of an access, until the next access occurs.

After a buffered write, there may be only a single address cycle between the two memory cycles. In this case, the next non-sequential address is broadcast in the last cycle of the previous access. This is the worst case for address decoding, as shown in Figure 11.3.

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