2.4. Debugger Signals

Table 2.4. Debugger signal descriptions

BREAKPOINTInBreakpointThis signal allows external hardware to halt execution of the processor for debug purposes. When HIGH, this causes the current memory access to be breakpointed. If memory access is an instruction fetch, the core enters debug state if the instruction reaches the execute stage of the core pipeline. If the memory access is for data, the core enters the debug state after the current instruction completes execution. This allows extension of the internal breakpoints provided by the EmbeddedICE module.
COMMRXOutCommunication Receive EmptyWhen HIGH, this signal denotes that the comms channel receive buffer is empty.
COMMTXOutCommunication Transmit EmptyWhen HIGH, this signal denotes that the comms channel transmit buffer is empty.
DBGACKOutDebug AcknowledgeWhen HIGH, this signal denotes that the ARM is in debug state.
DBGENInDebug EnableThis signal allows the debug features of ARM720T to be disabled. This signal should be LOW if debug is not required.
DBGRQInDebug RequestThis signal causes the core to enter debug state after executing the current instruction. This allows external hardware to force the core into debug state, in addition to the debugging features provided by the EmbeddedICE module.
EXTERN [1:0]InExternal ConditionThese signals allow breakpoints and/or watchpoints to depend on an external condition.
RANGEOUT[1:0]OutRange OutThese signals indicate that the relevant EmbeddedICE watchpoint register has matched the conditions currently present on the address, data and control buses. These signals are independent of the state of the watchpoint enable control bits.
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