8.2. Debug Systems

The ARM7DMT forms one component of a debug system that interfaces from the high‑level debugging performed by the user to the low-level interface supported by ARM7DMT. Such a system typically has three parts:

The Debug Host

This is a computer, for example a PC, running a software debugger such as ARMSD. The debug host allows the user to issue high level commands such as “set breakpoint at location XX”, or “examine the contents of memory from 0x0 to 0x100”

The Protocol Converter

The Debug Host is connected to the ARM7DMT development system via an interface (an RS232, for example). The messages broadcast over this connection must be converted to the interface signals of the ARM7DMT, and this function is performed by the protocol converter.


ARM7DMT, with hardware extensions to ease debugging, is the lowest level of the system. The debug extensions allow the user to stall the core from program execution, examine its internal state and the state of the memory system, and then resume program execution.

Figure 8.1. Typical debug system

The anatomy of ARM7DMT is shown in Figure 8.2. The major blocks are:


This is the CPU core, with hardware support for debug.


This is a set of registers and comparators used to generate debug exceptions (for example, breakpoints). This unit is described in Chapter 9 EmbeddedICE Macrocell.

TAP controller

This controls the action of the scan chains via a JTAG serial interface.

The Debug Host and the Protocol Converter are system dependent. The rest of this chapter describes the ARM7DMT’s hardware debug extensions.

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