11.6.2. BWAIT

The BWAIT pin can be used to extend memory accesses in whole cycle increments.

BWAIT is driven by the selected slave during the LOW phase of BCLK. When a slave cannot complete an access in the current cycle, it drives BWAIT HIGH to stall the ARM720T.

BWAIT does not prevent changes in BTRAN[1:0] and write data on BD[31:0] during the cycle in which it was asserted HIGH. Changes in these signals are then prevented until the BCLK HIGH phase after BWAIT was taken LOW. The addressing signals do not change from the rising BCLK edge when BWAIT goes HIGH, until the next BCLK HIGH phase after BWAIT returns LOW.

In Figure 11.4, the heavy bars indicate the cycle for which signals are stable as a result of asserting BWAIT.

The signal BTRAN[1:0] is pipelined by one bus cycle. This pipelining should be taken into account when these signals are being decoded. The value of BTRAN[1:0] indicates whether the next bus cycle is a data cycle or an address cycle.

As bus cycles are stretched by BWAIT, the boundary between bus cycles is determined by the falling edge of BCLK when BWAIT was sampled as LOW on the rising edge of BCLK. A useful rule of thumb is to sample the value of BTRAN[1:0] on the falling edge of BCLK only when BWAIT was LOW on the previous rising edge of BCLK.

When BWAIT is used to stretch a sequential cycle, BTRAN[1:0] returns to signalling address during the first phase of the sequential cycle if a single word access is occurring. In this case, it is important that the memory controller does not interpret that an address cycle is signalled when it is a stretched memory cycle.

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