2.5. Miscellaneous Signals

Table 2.5. Miscellaneous signal descriptions

NameTypeSource/DestinationDescription
BIGENDOut Configuration InputBig-endian FormatWhen this signal is HIGH, the processor treats bytes in memory as being in big-endian format. When it is LOW, memory is treated as little-endian.
FCLKInExternal Clock sourceFast Clock inputThis clock is used to clock the ARM core when Xfastbus is LOW. During testing, the signal allows efficient testing of the RAM, TAG and MMU blocks.
XFASTBUSInConfiguration InputBus clocking Mode Configuration SignalWhen HIGH the ARM720T operates from a single clock, BCLK. When LOW selects standard mode operating from two clocks, BCLK and FCLK.
XnFIQIn Interrupt controllerARM Fast Interrupt Request Signal
XnIRQInInterrupt controllerARM Interrupt Request SignalThe interrupt controller mixes several interrupt sources, and produces XnIRQ.
XSnAInConfiguration InputSynchronous/not Asynchronous Configuration PinIn standard ARM bus mode this signal determines the bus interface mode and should be wired HIGH or LOW depending on the desired relationship between FCLK and BCLK. See Standard Mode. This pin is ignored when operating with the fastbus extension.
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