11.2. Cycle Types

In normal operation, the ARM720T bus interface can perform two types of cycle:

These cycles are differentiated by the pipelined signal BTRAN[1:0]. Conventionally, cycles are considered to start from the falling edge of BCLK, and this is how they are shown in all diagrams.

Tese cycle types are a subset of the possible ASB cycle types. Other cycle types can be forced by the use of the Slave Response signals. See the AMBA Specification ARM IHI 0001 for more details.

The Addressing and Memory Request signals are pipelined ahead of the Data Addressing by a phase (1/2 a cycle), and BTRAN[1:0] by a cycle. This advance information allows the implementation of efficient memory systems.

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