11.4. Memory Request Signals

The memory request signals, BTRAN[1:0] are pipelined by one bus cycle, and refer to the next bus cycle.

Care must be taken when de-pipelining these signals if BWAIT is being used, as they always refer to the following bus cycle, rather than the following BCLK cycle. BWAIT stretches the bus cycle by an integer number of BCLK cycles. See BWAIT.

Table 11.1. BTRAN[1:0] Encoding

BTRAN[1:0]Cycle TypeDescriptionNote
00AddressAddress transfer or idle cycle 
01 Reserved 
10Non-SequentialNon-Sequential Data transfer cycle1
11SequentialSequential Data transfer cycle 
Note 1

This cycle can only occur as a result of the slave response signals. In normal operation, ARM720T does not generate this cycle type.

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E