11.7. Maximum Sequential Length

The ARM720T may perform sequential memory accesses whenever the cycle is of the same type as the previous cycle (for example, read/write), and the addresses are consecutive. However, sequential accesses are interrupted on a 256-word boundary.

If a sequential access is performed over a 256-word boundary, the access to word 256 is turned into a non-sequential access, and further accesses continue sequentially as before.

This simplifies the design of the memory controller. Provided that peripherals and areas of memory are aligned to 256‑word boundaries, sequential bursts are always local to one peripheral or memory device. This means that all accesses to a device always start with a non-sequential access.

A DRAM controller can take advantage of the fact that sequential cycles are always within a DRAM page, provided the page size is greater than 256.

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E