8.6. Public Instructions

The public instructions are listed below. In the descriptions that follow, TDI and TMS are sampled on the rising edge of TCK and all output transitions on TDO occur as a result of the falling edge of TCK.

EXTEST 0000

places the selected scan chain in test mode. This instruction connects the selected scan chain between TDI and TDO.

When the instruction register is loaded with EXTEST, all the scan cells are placed in their test mode of operation.

CAPTURE-DR

Inputs from the system logic and outputs from the output scan cells to the system are captured by the scan cells.

SHIFT-DR

The previously captured test data is shifted out of the scan chain via TDO, while new test data is shifted in via the TDI input. This data is applied immediately to the system logic and system pins.

SCAN_N 0010

connects the Scan Path Select Register between TDI and TDO. On reset, scan chain 3 is selected by default. The scan path select register is 4 bits long in this implementation, although no finite length is specified.

CAPTURE-DR

The fixed value 1000 is loaded into the register.

SHIFT-DR

The ID number of the desired scan path is shifted into the scan path select register

UPDATE-DR

The scan register of the selected scan chain is connected between TDI and TDO, and remains connected until a subsequent SCAN_N instruction is issued.

INTEST 1100

places the selected scan chain test mode. This instruction connects the selected scan chain between TDI and TDO.

When the instruction register is loaded with this instruction, all the scan cells are placed in their test mode of operation.

Single-step operation is possible using the INTEST instruction.

CAPTURE-DR

The value of the data applied from the core logic to the output scan cells, and the value of the data applied from the system logic to the input scan cells is captured.

SHIFT-DR

The previously captured test data is shifted out of the scan chain via the TDO pin, while new test data is shifted in via the TDI pin.

IDCODE 1110

connects the device identification register (or ID register) between TDI and TDO. The ID register is a 32-bit register that allows the manufacturer, part number and version of a component to be determined through the TAP. See ARM7DMT device identification (ID) code register for the details of the ID register format.

When the instruction register is loaded with this instruction, all the scan cells are placed in their normal (system) mode of operation.

CAPTURE-DR

The device identification code is captured by the ID register

SHIFT-DR

The previously captured device identification code is shifted out of the ID register via the TDO pin, while data is shifted in via the TDI pin into the ID register.

UPDATE-DR

The ID register is unaffected.

BYPASS 1111

connects a 1-bit shift register (the bypass register) between TDI and TDO.

When this instruction is loaded into the instruction register, all the scan cells are placed in their normal (system) mode of operation. This instruction has no effect on the system pins.

Note

All unused instruction codes default to the bypass instruction.

CAPTURE-DR

A logic 0 is captured by the bypass register.

SHIFT-DR

Test data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle. Note that the first bit shifted out is a zero.

UPDATE-DR

The bypass register is not affected.

CLAMP 0101

connects a 1-bit shift register (the bypass register) between TDI and TDO.

When this instruction is loaded into the instruction register, the state of all the output signals is defined by the values previously loaded into the currently loaded scan chain.

Note

This instruction should only be used when scan chain 0 is the currently selected scan chain.

CAPTURE-DR

A logic 0 is captured by the bypass register.

SHIFT-DR

Test data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle. Note that the first bit shifted out is a zero.

UPDATE-DR

The bypass register is not affected.

HIGHZ 0111

connects a 1-bit shift register (the bypass register) between TDI and TDO.

When this instruction is loaded into the instruction register, the Address bus, A[31:0], the data bus, D[31:0], plus nRW, nOPC, LOCK, MAS[1:0], and nTRANS are all driven to the high impedance state and the external HIGHZ signal is driven HIGH. This is as if the signal TBE had been driven LOW.

CAPTURE-DR

A logic 0 is captured by the bypass register.

SHIFT-DR

Test data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle. Note that the first bit shifted out is a zero.

UPDATE-DR

The bypass register is not affected.

CLAMPZ 1001

connects a 1-bit shift register (the bypass register) between TDI and TDO.

When this instruction is loaded into the instruction register, all the 3-state outputs (as described above) are placed in their inactive state, but the data supplied to the outputs is derived from the scan cells. The purpose of this instruction is to ensure that, during production test, each output can be disabled when its data value is either a logic 0 or a logic 1.

CAPTURE-DR

A logic 0 is captured by the bypass register.

SHIFT-DR

Test data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle. Note that the first bit shifted out will be a zero.

UPDATE-DR

The bypass register is not affected.

RESTART 0100

restarts the processor on exit from debug state. It connects the bypass register between TDI and TDO and the TAP controller behaves as if the bypass instruction had been loaded. The processor resynchronizes back to the memory system once the RUN-TEST/IDLE state is entered.

SAMPLE/PRELOAD 0011

Note

This instruction is included for production test only, and should never be used.

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