11.5. Data Signal Timing

During a read access, the data is sampled on the falling edge of BCLK at the end of the sequential cycle. During a write access, the data on BD[31:0] is timed off the falling edge of BCLK at the start of the memory cycle. If BWAIT is being used to stretch this cycle, the data is valid from the falling edge of BCLK at the end of the previous cycle, when BWAIT was HIGH. See BWAIT.


In a low‑power system, you must ensure that the databus is not allowed to float to an undefined level. This causes power to be dissipated in the inputs of devices connected to the bus. This is particularly important when a system is put into a low‑power sleep mode. It is recommended that one set of databus drivers in the system are left enabled during sleep to hold the bus at a defined level.

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E