12.4. RAM Test Mode

The RAM test mode is used to perform an intensive test of the RAM arrays, to provide full coverage of bit faults. In this test mode, the rest of the ARM720T is held in the reset and direct access is provided to the data, address and control signals of the RAM.

To accommodate this, an alternative test sequence is used, see Figure 12.3.

In this test mode, the RAM control signals are derived from unused address bits, as shown in Table 12.1.

To enter RAM test mode, bits 30 and 28 of the control packet should be set. This places the ARM720T into RAM test mode, and forces the RAM to be clocked from the FCLK input.

Figure 12.3. State machine for RAM test mode

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