12.6. MMU Test Mode

The MMU Test Mode is used to perform an intensive test of all the cells in the TLB array and to test the protection mechanism. In this test mode the rest of the ARM720T is held in reset and direct access is provided to the data, control and translated address of the MMU. See Figure 12.5.

In this test mode, the MMU Control Signals are derived from the MMU CM packet.

To enter MMU test mode, bits 28 and 27 of the control packet should be set. This places the ARM720T into MMU test mode and forces the MMU to be clocked from the FCLK input.

Figure 12.5. State machine for MMU test mode

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