12.5. TAG Test Mode

The TAG test mode is used to perform an intensive test of all of the cells of the TAG array, and to test the TAG comparators. In this test mode, the rest of the ARM720T is held in reset and direct access is provided to the data, address and control signals of the RAM. See Figure 12.4. In this test mode the TAG control signals are derived from the TAG CTL packet as shown in Table 12.2.

To enter TAG test mode, bits 29 and 28 of the control packet should be set. This places the ARM720T into TAG test mode, and forces the TAG to be clocked from the FCLK input.

Figure 12.4. State machine for TAG test mode

Table 12.2. TAG test mode TAG CTL packet bit positions

TAG CTL packet bitTAG signalDescription
[11:8]FLUSH[3:0]When asserted each bit flushes the appropriate TAG arrays
[7:4]TAGSEL[3:0]Tag select signal, each bit selects a TAG array
2WRITETAG write strobe
1READTAG read strobe
0VALIDValid input, the value on VALID is written into the valid cell in the array on a write.
Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E