12.3. ARM7DMT Core Test Mode

Table 12.1. RAM test mode address packet bit positions

Address packet bitRAM signalDescription
[24:23]MAS[1:0]RAM access size
22RSEQRAM sequential signal
21IMMEDImmediate write signal, controls write pipeline, and selects between RAMSEL[3:0] and SETSEL[3:0].
20WRITERAM write strobe
19READRAM read strobe
[18:15]RAMSEL[3:0]RAM bank select signal, used when IMMED is LOW
[14:11]SETSEL[3:0]RAM bank select signal, used when IMMED is HIGH
[10:0]ADDR[10:0]RAM address

The ARM7TDMI test places the ARM720T into a test mode so that the signals of the ARM7DMT are visible to the AMBA interface. In this mode, the rest of ARM720T is held in reset. The ARM720T is placed in the mode by setting bit 31 of the control register, see Table 12.4.

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