4.3. Registers

ARM720T contains registers which control the cache and MMU operation. These registers are accessed using CPRT instructions to Coprocessor #15 with the processor in a privileged mode.

Only some of registers 0 – 15 are valid. An access to an invalid register causes neither the access nor an undefined instruction trap, and therefore should never be carried out.

Table 4.1. Cache & MMU control register

RegisterRegister ReadsRegister Writes
0ID RegisterReserved
1ControlControl
2Translation Table BaseTranslation Table Base
3Domain Access ControlDomain Access Control
4ReservedReserved
5Fault StatusFault Status
6Fault AddressFault Address
7ReservedCache Operations
8ReservedTLB Operations
9 – 12ReservedReserved
13Process IDProcess ID
14 – 15ReservedReserved
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