4.3.2. Register 1: Control register

Reading from CP15 register 1 reads the control bits. The CRm and opcode_2 fields should be zero when reading CP15 register 1.

Figure 4.4. Register 1 read

Writing to CP15 register 1 sets the control bits. The CRm and opcode_2 fields should be zero when writing CP15 register 1.

Figure 4.5. Register 1 write

All defined control bits are set to zero on reset. The control bits have the following functions:

M Bit 0

MMU Enable/Disable

0 = Memory Management Unit (MMU) disabled

1 = Memory Management Unit (MMU) enabled

A Bit 1

Alignment Fault Enable/Disable

0 = Address Alignment Fault Checking disabled

1 = Address Alignment Fault Checking enabled

C Bit 2

Cache Enable/Disable

0 = Instruction and/or Data Cache (IDC) disabled

1 = Instruction and/or Data Cache (IDC) enabled

W Bit 3

Write buffer Enable/Disable

0 = Write Buffer disabled

1 = Write Buffer enabled

P Bit 4

When read, returns 1; when written, is ignored.

D Bit 5

When read, returns 1; when written, is ignored.

L Bit 6

When read, returns 1; when written, is ignored.

B Bit 7

Big-endian/Little-endian

0 = Little-endian operation

1 = Big-endian operation

S Bit 8

System protection

Modifies the MMU protection system.

R Bit 9

ROM protection

Modifies the MMU protection system.

Bits 31:14

When read, this returns an unpredictable value. When written, it should be zero, or a value read from these bits on the same processor. Note that using a read-write-modify sequence when modifying this register provides the greatest future compatibility.

V Bit 13

Location of exception vectors

0 = low addresses

1 = high addresses

The V bit can only be programmed if the WinCE Enhancements pin is at a logic “1”, that is, the WinCE Enhancements are enabled.

Enabling the MMU

Care must be taken if the translated address differs from the untranslated address, because the instructions following the enabling of the MMU will have been fetched using no address translation; enabling the MMU may be considered as a branch with delayed execution.

A similar situation occurs when the MMU is disabled. The correct code sequence for enabling and disabling the MMU is given in Interaction of the MMU, IDC and Write Buffer.

If the cache and write buffer are enabled when the MMU is not enabled, the results are unpredictable.

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