9.6. Debug Status Register

The Debug Status Register is 5 bits wide.

Figure 9.5. Debug status register format

The function of each bit in this register is as follows:

Bits 1 and 0

allow the values on the synchronized versions of DBGRQ and DBGACK to be read.

Bit 2

allows the state of the core interrupt enable signal (IFEN) to be read. As the capture clock for the scan chain may be asynchronous to the processor clock, the DBGACK output from the core is synchronized before being used to generate the IFEN status bit.

Bit 3

allows the state of the NMREQ signal from the core (synchronized to TCK) to be read. This allows the debugger to determine that a memory access from the debug state has completed.

Bit 4

allows TBIT to be read. This enables the debugger to determine what state the processor is in, and which instructions to execute.

The structure of the debug status register bits is shown in Figure 9.6.

Figure 9.6. Structure of TBIT, NMREQ, DBGACK, DBGRQ and INTDIS bits

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