9.1. Overview

In this chapter ARM7DMT refers to the ARM7TDMI core excluding the EmbeddedICE Macrocell. EmbeddedICE is programmed in a serial fashion using the ARM7DMT TAP controller. It consists of two real-time watchpoint units, together with a control and status register. One or both watchpoint units can be programmed to halt the execution of instructions by the ARM7DMT core via its BREAKPT signal.

Two independent registers, Debug Control and Debug Status, provide overall control of EmbeddedICE's operation. Figure 9.1 shows the relationship between the core, EmbeddedICE and the TAP controller.

Execution is halted when a match occurs between the values programmed into EmbeddedICE and the values currently appearing on the address bus, data bus and various control signals. Any bit can be masked so that its value does not affect the comparison.


Only those signals that are pertinent to EmbeddedICE are shown.

In the ARM720T, the EmbeddedICE module is connected directly to the ARM7DMT Core and therefore functions on the virtual address of the processor after relocation by the task ID.

Figure 9.1. ARM7TDMI block diagram

Either watchpoint unit can be configured to be a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). Watchpoints and breakpoints can be made to be data-dependent.

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E