9.5. The Debug Control Register

The Debug Control Register is 3 bits wide.

The function of each bit in this register is as follows:

Figure 9.4. Debug control register format

Bits 1 and 0 allow the values on DBGRQ and DBGACK to be forced.


As shown in Figure 9.6, the value stored in bit 1 of the control register is synchronized and then ORed with the external DBGRQ before being applied to the processor. The output of this OR gate is the signal DBGRQI which is brought out externally from the macrocell.

The synchronization between control bit 1 and DBGRQI is to assist in multiprocessor environments. The synchronisation latch only opens when the TAP controller state machine is in the RUN-TEST/IDLE state. This allows an enter debug condition to be set up in all the processors in the system while they are still running. Once the condition is set up in all the processors, it can then be applied to them simultaneously by entering the RUN-TEST/IDLE state.


In the case of DBGACK, the value of DBGACK from the core is ORed with the value held in bit 0 to generate the external value of DBGACK seen at the periphery of ARM7DMT. This allows the debug system to signal to the rest of the system that the core is still being debugged even when system-speed accesses are being performed (in which case, the internal DBGACK signal from the core will be LOW).


If bit 2 (INTDIS) is asserted, the interrupt enable signal (IFEN) of the core is forced LOW. Thus all interrupts (IRQ and FIQ) are disabled during debugging (DBGACK =1) or if the INTDIS bit is asserted. The IFEN signal is driven according to the following table:

Table 9.3. IFEN signal control

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