10.3. Standard Mode

Using the standard mode of operation (without the fastbus extension), and FASTBUS tied LOW, the ARM720T has two input clocks:

The bus interface is always controlled by the memory clock, BCLK, qualified by BWAIT. However, the core and cache are clocked by the fast clock, FCLK.

In standard mode, the FCLK frequency must be greater than or equal to the BCLK frequency at all times. This relationship must be maintained on a cycle‑by‑cycle basis.

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E
Non-Confidential