3.6.10. Exception priorities

When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled:

  1. Reset (Highest priority)

  2. Data abort

  3. FIQ

  4. IRQ

  5. Prefetch abort

  6. Undefined Instruction, Software interrupt (Lowest priority)

Exception restrictions

Undefined Instruction and Software Interrupt are mutually exclusive, because they each correspond to particular (non-overlapping) decodings of the current instruction.

If a data abort occurs at the same time as a FIQ, and FIQs are enabled (that is, the CPSR’s F flag is clear), ARM720T enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ causes the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations.

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