7.2. MMU Program Accessible Registers

The ARM720T Processor provides several 32-bit registers which determine the operation of the MMU. These are described in Memory Formats.

Data is written to and read from the MMU's registers using the ARM CPU's MRC and MCR coprocessor instructions.

A brief description of the registers is provided below. Each register is discussed in more detail within the section that describes its use.

Table 7.1. MMU program accessible registers

Translation Table Baseholds the physical address of the base of the translation table maintained in main memory. Note that this base must reside on a 16KB boundary.
Domain Access Controlconsists of sixteen 2-bit fields, each of which defines the access permissions for one of the sixteen Domains (D15–D0).
TLB Operationsallows individual or all TLB entries to be marked as invalid.
Fault Status

indicates the domain and type of access being attempted when an abort occurred.

Bits [7:4]

specify which of the sixteen domains (D15-D0) was being accessed when a fault occurred.

Bits [3:1]

indicate the type of access being attempted.

The encoding of these bits is different for internal and external faults (as indicated by bit 0 in the register) and is shown in Table 7.5.

Fault Addressholds the virtual address of the access which was attempted when a fault occurred.

The Fault Status Register and Fault Address Register are only updated for data faults, not for prefetch faults.

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