7.11. MMU Faults and CPU Aborts

The MMU generates four types of faults:

In addition, an external abort may be raised on external data access.

The access control mechanisms of the MMU detect the conditions that produce these faults. If a fault is detected as the result of a memory access, the MMU aborts the access and signals the fault condition to the CPU. The MMU is also capable of retaining status and address information about the abort. The CPU recognises two types of abort which are treated differently by the MMU:

If the MMU detects an access violation, it does so before the external memory access takes place, and it therefore inhibits the access. External aborts do not necessarily inhibit the external access, as described in the section on external aborts.

If the ARM720T is operating in fastbus mode an internally aborting access may cause the address on the external address bus to change, even though the external bus cycle has been cancelled. The address that is placed on the bus is the translation of the address that caused the abort, though in the case of a Translation Fault the value of this address is undefined. No memory access is performed to this address.

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