7.16. Interaction of the MMU, IDC and Write Buffer

The MMU, IDC and WB may be enabled/disabled independently. However, in order for the write buffer or the cache to be enabled the MMU must also be enabled. There are no hardware interlocks on these restrictions, so invalid combinations cause undefined results

Table 7.7. Valid MMU, IDC and write buffer combinations

MMUIDCWB
offoffoff
onoffoff
ononoff
onoffon
ononon

The following procedures must be observed.

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