7.6. Section Descriptor

C (Cacheable):

indicates that data at this address is placed in the cache (if the cache is enabled).

B (Bufferable):

indicates that data at this address is written through the write buffer (if the write buffer is enabled).

Note

The meaning of the C and B bits may change in later ARM processors. It is strongly recommend that you structure software so that code which manipulates the MMU page tables is contained in a single module. It can then be updated easily when you port it to a different ARM processor.

Bits [3:2] (C, B)

control the cache- and write-buffer-related functions.

Bit [4]

should be written to 1 for backward compatibility.

Bits [8:5]

specify one of the 16 possible domains (held in the Domain Access Control Register) that contain the primary access controls.

Bits [11:10] (AP)

specify the access permissions for this section and are interpreted as shown in Table 7.3. Their interpretation depends on the setting of the S and R bits (control register bits 8 and 9). The Domain Access Control specifies the primary access control; the AP bits only have an effect in client mode. Refer to Domain Access Control.

Bits [19:12]

are always written as 0.

Bits [31:20]

form the corresponding bits of the physical address for the 1MB section.

Table 7.3. Interpreting access permission (AP) bits

APSRSupervisor Permission User Permission Notes
0000No AccessNo Access Any access generates a permission fault
0010Read OnlyNo AccessSupervisor Read Only permitted
0001Read OnlyRead OnlyAny write generates a permission fault
0011ReservedReservedReserved
01 xxRead/WriteNo Access Access allowed only in Supervisor mode
10xxRead/WriteRead Only Writes in User mode cause permission fault
11xxRead/WriteRead/Write All access types permitted in both modes.
xx11ReservedReservedReserved
Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E
Non-Confidential