7.12. Fault Address and Fault Status Registers (FAR & FSR)

Aborts resulting from data accesses (data aborts) are acted upon by the CPU immediately, and the MMU places an encoded 4-bit value FS[3:0], along with the 4‑bit encoded Domain number, in the Fault Status Register (FSR).

In addition, the virtual processor address which caused the data abort is latched into the Fault Address Register (FAR). If an access violation simultaneously generates more than one source of abort, they are encoded in the priority given in Table 7.2.

Table 7.5. Priority encoding of fault status

 SourceFS[3210]Domain[3:0]FAR
HighestAlignment00x1invalidvalid
 

Bus Error (translation) level1

level2

1100

1110

invalid

valid

valid

valid

 

Translation Section

Page

0101

0111

invalid

valid

valid

valid

 

Domain Section

Page

1001

1011

valid

valid

valid

valid

 

Permission Section

Page

1101

1111

valid

valid

valid

valid

 

Bus Error (linefetch) Section

Page

0100

0110

valid

valid

Note 2

Note 2

Lowest

Bus Error (other) Section

Page

1000

1010

valid

valid

valid

valid

x is undefined, and may read as 0 or 1.

Notes
  1. Any abort masked by the priority encoding may be regenerated by fixing the primary abort and restarting the instruction.

  2. The FAR contains the address of the start of the linefetch.

CPU instructions are prefetched, so a prefetch abort simply flags the instruction as it enters the instruction pipeline. Only when (and if) the instruction is executed does it cause an abort; an abort is not acted upon if the instruction is not used (that is, it is branched around). Because instruction prefetch aborts may or may not be acted upon, the MMU status information is not preserved for the resulting CPU abort. For a prefetch abort, the MMU does not update the FSR or FAR.

The sections that follow describe the various access permissions and controls supported by the MMU and detail how these are interpreted to generate faults.

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