1.4.1. ARM instruction set

This section gives an overview of the ARM instructions available. For full details of these instructions, please refer to the ARM Architecture Reference Manual (ARM DDI 0100).

Format summary

The ARM instruction set formats are shown below.

Figure 1.2. ARM instruction set formats


Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken; for example, a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations.

ARM instruction summary

The following table summarizes the ARM instruction set

Table 1.1. ARM instruction summary

ADCAdd with Carry
Rd := Rn + Op2 + Carry
Rd := Rn + Op2
Rd := Rn AND Op2
R15 := address
BICBit Clear
Rd := Rn AND NOT Op2
BLBranch with Link
R14 := R15, R15 := address
BXBranch and Exchange
R15 := Rn,
T bit := Rn[0]
CDPCoprocessor Data Processing(Coprocessor-specific)
CMNCompare Negative
CPSR flags := Rn + Op2
CPSR flags := Rn - Op2
EORExclusive OR
Rd := (Rn AND NOT Op2)
OR (op2 AND NOT Rn)
LDCLoad Coprocessor from MemoryCoprocessor load
LDMLoad Multiple RegistersStack manipulation (Pop)
LDRLoad Register from Memory
Rd := (address)
MCRMove CPU Register to Coprocessor Register
cRn := rRn {<op>cRm}
MLAMultiply Accumulate
Rd := (Rm * Rs) + Rn
MOVMove Register or Constant
Rd : = Op2
MRCMove from Coprocessor Register to CPU Register
Rn := cRn {<op>cRm}
MRSMove PSR Status/Flags to Register
Rn := PSR
MSRMove Register to PSR Status/Flags
PSR := Rm
Rd := Rm * Rs
MVNMove Negative Register
Rd := Rn OR Op2
RSBReverse Subtract
Rd := Op2 - Rn
RSCReverse Subtract with Carry
Rd := Op2 - Rn - 1 + Carry
SBCSubtract with Carry
Rd := Rn - Op2 - 1 + Carry
STCStore Coprocessor Register to Memory
address := CRn
STMStore Multiple Stack manipulation (Push)
STRStore Register to Memory
<address> := Rd
Rd := Rn - Op2
SWISoftware InterruptOS call
SWPSwap Register with Memory
Rd := [Rn], [Rn] := Rm
TEQTest Bitwise Equality
CPSR flags := Rn EOR Op2
TSTTest Bits
CPSR flags := Rn AND Op2
Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E