3.5.2. The control bits

The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These change when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software.

I and F bits

are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively.

The T bit

reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal. Software must never change the state of the TBIT in the CPSR. If this happens, the processor then enters an unpredictable state.

M[4:0] bits

are the mode bits. These determine the processor’s operating mode, as shown in Table 3.2. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used.

Note

If any illegal value is programmed into the mode bits, M[4:0], then the processor then enters an unrecoverable state. If this occurs, reset should be applied.

Reserved bits

The remaining bits in the PSRs are reserved. When changing a PSR’s flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on their containing specific values, since in future the processors they may read as one or zero.

Table 3.2. PSR mode bit values

M[4:0]ModeVisible THUMB state registersVisible ARM state registers
10000User
R7..R0,
LR, SP
PC, CPSR
R14..R0,
PC, CPSR
10001FIQ
R7..R0,
LR_fiq, SP_fiq
PC, CPSR, SPSR_fiq
R7..R0,
R14_fiq..R8_fiq,
PC, CPSR, SPSR_fiq
10010IRQ
R7..R0,
LR_irq, SP_irq
PC, CPSR, SPSR_irq
R12..R0,
R14_irq..R13_irq,
PC, CPSR, SPSR_irq
10011Supervisor
R7..R0,
LR_svc, SP_svc,
PC, CPSR, SPSR_svc
R12..R0,
R14_svc..R13_svc,
PC, CPSR, SPSR_svc
10111Abort
R7..R0,
LR_abt, SP_abt,
PC, CPSR, SPSR_abt
R12..R0,
R14_abt..R13_abt,
PC, CPSR, SPSR_abt
11011Undefined
R7..R0
LR_und, SP_und,
PC, CPSR, SPSR_und
R12..R0,
R14_und..R13_und,
PC, CPSR
11111System
R7..R0,
LR, SP
PC, CPSR
R14..R0,
PC, CPSR
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