3.6.1. Action on entering an exception

When handling an exception, the ARM720T:

  1. Preserves the address of the next instruction in the appropriate Link Register.

    • If the exception has been entered from ARM state, the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the exception—see Table 3.3 for details).

    • If the exception has been entered from THUMB state, the value written into the Link Register is the current PC, offset by a value such that the program resumes from the correct place on return from the exception. This means that the exception handler need not determine which state the exception was entered from.

    For example, in the case of SWI:

    MOVS PC, R14_svc

    always returns to the next instruction regardless of whether the SWI was executed in ARM or THUMB state.

  2. Copies the CPSR into the appropriate SPSR.

  3. Forces the CPSR mode bits to a value which depends on the exception.

  4. Forces the PC to fetch the next instruction from the relevant exception vector.

It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions.

If the processor is in THUMB state when an exception occurs, it automatically switches into ARM state when the PC is loaded with the exception vector address.

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