3.6.3. Exception entry/exit summary

Table 3.3 summarises the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler.

Table 3.3. Exception entry/exit

ExceptionReturn Instruction                  Previous StateNote
ARM R14_xTHUMB R14_x
BLMOV PC, R14PC + 4PC + 21
SWIMOVS PC, R14_svcPC + 4PC + 21
UDEFMOVS PC, R14_undPC + 4PC + 21
FIQSUBS PC, R14_fiq, #4PC + 4PC + 42
IRQSUBS PC, R14_irq, #4PC + 4PC + 42
PABTSUBS PC, R14_abt, #4PC + 4PC + 41
DABTSUBS PC, R14_abt, #8PC + 8PC + 83
RESETNA--4

Notes

  1. Where PC is the address of the BL/SWI/Undefined Instruction fetch that had the prefetch abort.

  2. Where PC is the address of the instruction that was not executed since the FIQ or IRQ took priority.

  3. Where PC is the address of the Load or Store instruction which generated the data abort.

  4. The value saved in R14_svc upon reset is unpredictable.

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